In a conventional computer system, messages are sent to and from various memories and interfaces. For example, the processor interface transmits messages to the memory/directory interface. However, the message receiver does not always have available space to receive the sender's message. One system for ensuring that the receiver has sufficient space for receiving the message is for the sender to request a grant from the receiver prior to sending the message. If space is available for the message, the sender is granted permission to send the message. Such a system has an inherent delay while the availability of the grant is determined.
An alternative system utilizes the concept of a credit mechanism. In a credit mechanism system, grants are made ahead of requests and are stored up so that there is no delay in determining whether a grant is available. In a credit system, the message sender and message receiver each have a counter. The sender counter tracks how many resources the sender knows are available. The receiver counter tracks how many resources are available that it has not yet told the sender about. The messages are received in a first-in-first-out (FIFO) buffer of the receiver where the messages await arbitration and a slot in memory. For example, the FIFO buffer may be sixteen slots deep and the arbitration queue may have 64 slots.
When the sender receives a signal such as a pulse from the receiver that the receiver has space in the FIFO buffer for a message, the sender counter is incremented. The pulse from the receiver represents one credit. When the sender counter is greater than zero, the sender can send a message. Upon the sender sending a message, the sender counter is decremented by one credit.
When the receiver counter is greater than zero, the receiver sends a pulse to the sender (which as described above causes the sender counter to be incremented) and decrements the receiver counter. In other words, the receiver transferred a credit to the sender. When a message is removed from the FIFO buffer into the arbitration queue, the receiver counter is incremented, representing an additional credit that is available but that has not yet been transmitted to the sender.
Computer systems, however, often need to send multiple message types with different resource utilization patterns and thus would require a different type of credit for each message type and either a complex channel or multiple channels for transmitting credits and messages, adversely affecting both latency and bandwidth.